IQINTRINSIC QUALITY, INC.

Design For Test Guidelines

Overview

Design for Test is about money. It has been repeatedly demonstrated that use of "bed of nails" in-circuit test (ICT) provides the most cost effective method of shipping most Electronic products. This statement is so overwhelmingly true that a simplifying assumption could be that any Electronic product should be considered a candidate for ICT. The design for this likely event (or lack thereof) will impact two things: 1) the cost of ICT, and 2) the quality of ICT.

Considering the cost issues, a starting place for implementing ICT is $10,000. More or less depending on the complexity of the task. Maybe split 60/40 with software being higher. If software development cost $100+ per hour, then ignoring the tasks of the test engineer, can have immediate consequences in price. Similarly ignoring the guidelines that enable low cost bed of nails fixtures, can easily double the cost of the fixture.

Of equal concern is the quality of test issues. ICT is so effective because it does two things well: it offers a high degree of assurance that passing products are indeed "good," and if a product fails the ICT diagnosis significantly aids repair. Failure to attend to Design for Test can destroy both the assurance of goodness and the ability to accurately diagnose.

Design for Test need not be viewed as a terrible burden. Like most elements of a discipline it can (and should) just become a regular part of the task definition. If it is incorporated into the workflow rather than tacked on at the end, it will get done without seeming too painful.

The guidelines are just guidelines. They can be ignored, or intentionally disregarded. There will need to be value judgments about their costs.

Guidelines

Circuit Design

1. Control Pins: Do not connect IC control pins ( Set, Reset, CE, OE, Etc) directly to power or ground. Use pull-ups or pull downs instead. Often tests of not only these devices but subsequent stages of logic will require tester control of these features.

2. Oscillators and Clocks: Provide some mechanism whereby clock signals can be reliably turned off by logic. At ICT, with the board powered up, running clocks create a chaos of noise for the test engineer.

3. Feedback Loops: Provide some mechanism so that digital feedback loops can be turned off. ICT systems use brief bursts of overdriving logic outputs. It is much easier to overdrive a static logic state that one dynamically changing.

4. High Current Devices: Provide some mechanism to turn off devices that have subsequent levels of logic. Tester backdrive capability is limited. Testing downstream devices may be impaired by high current drivers.

5. Complex and Custom Devices: Complex devices that are not likely to have "library" tests routines need special considerations. One simple approach is Boundary Scan. Another is some form of BIST. At the very least, consideration should be given to a mechanism for disabling the device so that even if untested, it doesn’t impede other tests. Not testing a device often has little consequence to the quality of the board test. But the test engineer needs a means to turn the device off.

6. Provide high quality Schematics, net lists, device programming files and BOMs. The test engineer will be responsible to make the board actually work in a fairly hostile environment. (The board probably wasn’t designed to run on a bed of nails with dozens of three-foot wires dangling.) Any assistance by way of good documentation will be greatly appreciated by test engineering.

PCB Physicals

1. Provide a probe-able pad for every net.

a. Strong preference to bottom side only. Topside probing can double the fixturing cost and add handling complexity.

b. Vias and through holes are fine.

c. Test Pad size at a minimum of .035"diameter. Smaller test Pads increase cost and reduce test reliability.

d. Test Pads spacing desired at .100" if possible. Slightly more costly is .075" spacing. Pads at .050" spacing are achievable but expensive. Less than .050" may be possible but is exotic.

e. Vias intended for test should not be covered with a solder mask.

f. Clearance from a test pad to a nearby conductor should be at least .020".

g. Clearance from a test pad to a nearby component should be at least .050".

2. Vias that are under bottom side components cannot be used as test pads.

3. Provide non-plated through tooling holes (diameter> .125") on diagonally opposite corners of the PCB. Topside components should not obscure access. Don’t use breakoff PCB surrounds. The ICT may be used for repair of returns.

4. Test Pads should be no closer than .100" to edge of PCB.

5. Bottom side parts that are over .125" tall may require milled relief in fixture plates. If possible minimize large bottom side components.

6. Tall bottom side parts that require milling may shadow surrounding test pads. The larger the uncertainty of part location, the larger the clearance to surrounding tests pads.

7. Vacuum actuated fixtures are often the most economical alternative. Ideally boards should be designed with all vias soldered closed and a minimum of open through holes. Swiss cheese boards will add about $1000 to the cost of a fixture.

8. Test Pads should be geographically distributed evenly across the area of the board. Ideally even distribution balances even air pressure in a vacuum fixture.

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Intrinsic Quality, Inc.

1855D Rohlwing Rd.

Rolling Meadows, IL 60008

847-259-5060 email: info@intrinsicquality.com